[Libre-soc-dev] daily kan-ban update 30oct2020

Cesar Strauss cestrauss at gmail.com
Fri Oct 30 23:15:47 GMT 2020

Last month

* Tested a bug fix in cxxsim. Input signals greater than 32 bits are now
working properly.

* Tracked down another cxxsim bug, and produced a reduced test case for it.

The issue, this time, is about not initializing signals declared with
"reset=1". So, for instance, the "shadown" inputs of computation units
are being kept active, at zero.

I will test the fix when it arrives.


* Helped Cole and Luke with a JTAG unit test issue.


* Created an OperandProducer class, for testing the Computation Units.


Since it seems to be the first use of "yield Passive()" in libre-soc,
I'll make a comment on it.

What it does, is to automatically terminate the corresponding process
when all the other "normal" (active by default) processes terminate.

It is useful in this case because the process is basically an infinite
loop, monitoring and reacting to a signal in the DUT. In fact, it could
have easily been implemented in nMigen RTL.

So, "yield Passive()" is potentially useful when replacing a RTL module
with an equivalent Python process.

Next week

* Apply the new OperandProducer class to the rest of the CompUnit unit

* Start adding formal verification to the CompUnits.

I feel that the Computation Units are pretty complex, with their
interlocked stages, multiple inputs and outputs, handshakes, etc. It is
a bit onerous to keep adding asserts, at every step, to the unit tests.
Formal verification is a better way of handling this, I think.



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