[Libre-soc-dev] daily kan-ban update 15oct2020

[Cole Poirier]

On Fri, Oct 16, 2020 at 2:54 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> On Fri, Oct 16, 2020 at 10:47 PM Cole Poirier <colepoirier at gmail.com> wrote:
>
> > Is the following sequence correct?
> >
> > ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55
>
> redundant.  waste of time, interferes.
>
> > ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --build
>
> correct.
>
> > ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --load
>
> correct.

Correction here for the list archive. I should have put
--sys-clk-freq=55e6 not simply -sys-clk-freq=55... dumb assumption on
my part that the Xe6 was implicit. Thankfully as soon as I tried to
run ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --build it
failed with an assertion error because duh 55 isn't above the clock
threshold :)

Cole