[Libre-soc-dev] daily kan-ban update 15oct2020

Cole Poirier colepoirier at gmail.com
Fri Oct 16 23:16:05 BST 2020

On Fri, Oct 16, 2020 at 2:54 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> redundant.  waste of time, interferes.

Ok cool, helpful, thank you.

> correct.

> correct.

Great. Getting an error trying to run make run_sim which is the
easiest way for me to generate libresoc.v:
INFO:SoCBusHandler:ics added as Bus Slave.
Traceback (most recent call last):
  File "src/soc/litex/florent/sim.py", line 480, in <module>
  File "src/soc/litex/florent/sim.py", line 469, in main
    soc = LibreSoCSim(cpu=args.cpu, debug=args.debug)
  File "src/soc/litex/florent/sim.py", line 129, in __init__
    gpio_wb = self.cpu.simple_gpio
  File "/home/colepoirier/src/migen/migen/fhdl/module.py", line 136,
in __getattr__
    raise AttributeError("'"+self.__class__.__name__+"' object has no
attribute '"+name+"'")
AttributeError: 'LibreSoC' object has no attribute 'simple_gpio'
make: *** [Makefile:22: run_sim] Error 1

Is this possibly because some command line options need to be
specified when calling issuer_verilog.py? I tried running with
--enable-testgpio and got the same exact error as above which runs
issuer_verilog.py without any command line options.


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