[Libre-soc-dev] daily kan-ban update 15oct2020

[Luke Kenneth Casson Leighton]

On Fri, Oct 16, 2020 at 10:47 PM Cole Poirier <colepoirier at gmail.com> wrote:

> Is the following sequence correct?
>
> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55

redundant.  waste of time, interferes.

> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --build

correct.

> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --load

correct.