[Libre-soc-dev] daily kan-ban update 15oct2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Oct 16 22:54:06 BST 2020

On Fri, Oct 16, 2020 at 10:47 PM Cole Poirier <colepoirier at gmail.com> wrote:

> Is the following sequence correct?
> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55

redundant.  waste of time, interferes.

> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --build


> ./versa_ecp5.py --fpga ulx3s85f --sys-clk-freq=55 --load


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