[Libre-soc-dev] daily kan-ban update 15oct2020

Cole Poirier colepoirier at gmail.com
Fri Oct 16 22:37:12 BST 2020

On Fri, Oct 16, 2020 at 1:45 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> maybe.  2 unknowns minimum.  except: i just got versa_ecp5 built 15
> mins ago.  i'll run it...  might as well do it now... and it works.
> you _might_ not need to set the sys-clk-freq to 55e6.  but do it anyway.

Will do, running pywriter.py now, then will run issuer_verilog.py,
then will test the fpga load with --sys-clk-freq=55.


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