[Libre-soc-dev] pia as cycle accurate simulator?

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Oct 15 18:23:32 BST 2020

crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Thu, Oct 15, 2020 at 6:10 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> it's not that hard, just tedious. I could have a working simulator for the
> instructions currently implemented up in 2-3 days.

i'd forgotten Jacob that we've got both Alain and Lauri involved,
here.  expertise:

* you - c, c++, rust, python, assembler
* me - c, c++, python, assembler - 25+ years
* alain - c, assembler - 40+ years
* lauri - c, c++, python(?), assembler

basically you would become the sole exclusive critical dependency for
the development and ongoing maintenance of a rust-based simulator.
neither Alain, Lauri nor myself could usefully contribute just when
it's critical to get things moving.

> * ISAcaller - part of LibreSOC - "does the job", is cycle-accurate, in
> > python is relatively slow, however has the advantage of being
> > co-developed with the HDL.
> >
> iirc it just executes everything in one cycle and doesn't keep track of
> cycles, so, if that counts as cycle accurate, it would be trivial to add
> that level of cycle accuracy to a pia-based simulator.

cycle-accurate means that when you do one "tick" of the clock, the
underlying simulator also does one "tick" such that when you do debug
printouts of the registers... or that you *can* do debug printouts of
the registers at all - it's clock-for-clock.  one "step" of the
simulator IS one "step" of the underlying state.

JIT simulators such as qemu utterly break and completely ignore that.
one step of the simulator will result in a bunch of completely
arbitrary and unknown native assembly code being executed, where you
have absolutely no idea what it did or why it did it, you cannot
necessarily get at the "host" (simulated) registers, and the JIT
engine will actually go and optimise and merge multiple "simulated"
assembly instructions into host (JIT compiled) instructions that
absolute zero relation or connection to the original.

JIT compilers are therefore great performance but a massive hindrance
to actual ISA development.


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