[Libre-soc-dev] New AMD GPU BW Enhancing Shared L1 Cache

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Oct 7 04:45:47 BST 2020

On 10/7/20, Cole Poirier <colepoirier at gmail.com> wrote:

> Cool! Although I think this implementation deals with a NoC algorithm
> too... Worth raising a bug report? Or just taking a look at it once we
> start doing SMP work?

yes because the organisation gives huge additional savings.  although
it is designed for massive interconnect (1000 cores) rather than
embedded level i.e. 4 to 8 cores

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