[Libre-soc-dev] New AMD GPU BW Enhancing Shared L1 Cache

Cole Poirier colepoirier at gmail.com
Wed Oct 7 02:30:13 BST 2020

On Tue, Oct 6, 2020 at 3:45 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> the idea appears to be to reconfigure L1 caches to be shared or
> private depending on workload and thus reduce bandwidth pressure on
> L2.
> shared L1.  that'll be a bundle of fun.  it might be practical to do
> by sharing access to individual *blocks* of the L1 SRAM (there are
> currently 4 "ways".  if each "way" can be made shared that would do
> the trick).

Cool! Although I think this implementation deals with a NoC algorithm
too... Worth raising a bug report? Or just taking a look at it once we
start doing SMP work? I have added the url to the youtube video and
the url to the pdf on the resources page of the wiki.


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