[Libre-soc-dev] efficient decoding algorithm for variable-length instructions

Luke Kenneth Casson Leighton lkcl at lkcl.net
Thu Nov 26 04:26:28 GMT 2020

jacob the imtermingling of 1st and 2nd level decoding (xo test) is
something that specifically cannot be done.  the toplevel FSM on the
raw insn stream has to be kept as absolute-basic as possible.

in addition just as with how SVP64 must not be intermingled with v3.1B
64 bit, SVP48 11 bit prefixes must not be intermingled with attn.

to try to go "err all 11 bit prefix combinations are permitted oh
except err if it happens to be the exact same encoding as if an attn
instruction was overlapping us" is asking for trouble.

and, just as with SVP64 if IBM decides to add extra instructions
beyond attn to the EXT000 space we're screwed.

best nip that in the bud and say "nope, attn is eliminated and moved elsewhere".

sc and scv can also likewise be moved in order to free up EXT017
because they are static 3bit patterns (no parameters).

what on earth they're doing taking up an entire major opcode is anybody's guess.

mulli, twi and tdi are harder to place elsewhere..  Paul supposed that
it would be reasonable to use the td and tw variants and just
eliminate twi and tdi entirely, giving another 2 free contiguous

mulli is tougher as it is used not a huge amount but not insignificant
either however can be moved to EXT005 or EXT021 if determined
worthwhile to keep.

lq goes.

vector goes (freeing up a ton of Majors)

v3.1B 64 bit moves to EXT005.

bear in mind this is all under "LibreSOC mode" so recompilation is a given.


   case 0: // 32/48-bits
        // check for bit set by "Support Processor Attention" instruction
        if((xo_field & 256) == 0) {
            mode_was_standard.size = 6; // 48-bit
            mode_was_standard_once_then_compressed.size = 6;
        } else {
            // SVP32 or "Support Processor Attention"
            // leave sizes as 32-bit

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