[Libre-soc-dev] soclayout/experiments10 doDesign.py

Cole Poirier colepoirier at gmail.com
Wed Nov 4 17:13:49 GMT 2020

On Wed, Nov 4, 2020 at 3:17 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> Cole, remember i said, "raise a bugreport and list the exact versions
> of git checkouts for all 3 repositories, and raise it on *our*
> bugtracker so as not to distract Jean-Paul?"

Sorry I thought so long as I didn't raise a bug report on JP's gitlab
that was ok, I didn't realize I had to not talk about it on our
mailing list in order to not distract JP.

> i can do front-line support so that you're not distracted, Jean-Paul.
> if i really can't sort it *then* we ask for your help.

I was just trying to figure out how the overall system/process works
so that I can understand how the chip gets placed and routed. JP is
correct that I was trying to run experiments9, I didn't realize that
subsequent experiments are mutually incompatible. I only asked here
because I got the same error message about VHDL instances mismatch
that you got and mentioned in the bug report on JP's gitlab instance
that you directed me to on this mailing list thread.


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