[Libre-soc-dev] soclayout/experiments10 doDesign.py
Jean-Paul.Chaput at lip6.fr
Wed Nov 4 09:05:28 GMT 2020
I don't know how you get there, but one thing is sure, you
shouldn't use "doChip.py" anymore with that example.
Only "doDesign.py" must be called.
The message in itself is a somewhat contrived way to say
that some pins of the models are unaffected (dangling).
Are you sure it's experiment10 ? And not experiment9 ?
(there shouldn't be any ls180.vst in 10)
On Tue, 2020-11-03 at 22:52 -0800, Cole Poirier wrote:
> Running into the same error as a see on issue #30 but I can't figure
> out how you solved it.
> [ERROR] CParsVst() VHDL Parser - File:<./ls180.vst> Line:100531
> Port map assignment discrepency instance:0 vs. model:1
> Python stack trace:
> #0 in <module>() at
> Libre-soc-dev mailing list
> Libre-soc-dev at lists.libre-soc.org
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