[Libre-soc-dev] soclayout/experiments10 doDesign.py

Cole Poirier colepoirier at gmail.com
Wed Nov 4 06:52:18 GMT 2020

Running into the same error as a see on issue #30 but I can't figure
out how you solved it.

[ERROR] CParsVst() VHDL Parser - File:<./ls180.vst> Line:100531
        Port map assignment discrepency instance:0 vs. model:1
        Python stack trace:
        #0 in                  <module>() at


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