Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Dec 17 23:32:17 GMT 2020
On Thursday, December 17, 2020, Jacob Lifshay <programmerjake at gmail.com>
> On Thu, Dec 17, 2020, 14:37 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
>> On Thursday, December 17, 2020, Jacob Lifshay <programmerjake at gmail.com>
>> the reason is: if it is not, and the encoding of all 0s happens to be
>> and that happens to be SUBVL=4, predicate=Xxx blah blah
>> then what will happen on a v3.B POWER10 system that does not have SV?
>> *no trap will be raised and the standard instruction will be executed*.
> no, an illegal instruction trap will occur, since those encodings are
> specifically defined in the OpenPower v3.1 spec to be illegal instructions
> -- not an invalid variation of a defined instruction. There *is no*
> corresponding standard instruction to be executed.
... because bits 6 and 9 are still set (constant 1). got there in the end.
>> > You don't need to specially turn VL off, it's just ignored if all
>> > inputs/outputs are set to scalar mode.
>> and predication is off, and ffirst is off, and elwidth is default etc
>> i actually have difficulty describing this, because in the pseudocode,
>> simulator *and* HDL, when VL=1 SUBVL=1 elwidth=default predicates=all1s
>> etc. there are two ways to view this:
>> * SV is "disabled" or
>> * every augmentation feature does nothing even the for-loops are for i in
>> range(1) and whilst SV is technically still active it isn't actually
>> *yet it is still running*. which is very weird, and i have no idea how
>> succinctly put this.
> SV is active, since you just executed an instruction from the SVP64
> instruction block. that instruction just so happens to have identical
> effect to the non-prefixed version,
the word which best matches is:
present but not visible, apparent, or actualized; existing as potential:
> but that doesn't matter here. This is
> just like how you could execute `fmv f3, f3` which has equivalent effect
> `nop` but it is not `nop`, it is a fp instruction.
ah except that's not quite what i meant. or, it is misleading... ish. take
addi r3, r7, 5, when SV is latent it's the exact same instruction whether
in v3.0B 32 bit or whether in the v3.1B SV 64 bit prefix with all 24 bits
btw i'd prefer it be all zeros because it nakes it easier and clearer to
understand and talk about.
i.e. if we say "there's this arbitrary bitpattern which if you set in the
24 bits, SV is latent" we are going to get some puzzled looks .
the concept "zero" being "nothing", if on the other hand we explain, "when
all zero, SV is latent i.e. has no effect" then the reaction will be more,
"oh i see".
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