[Libre-soc-dev] svp64

Jacob Lifshay programmerjake at gmail.com
Thu Dec 17 22:51:01 GMT 2020

On Thu, Dec 17, 2020, 14:37 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Thursday, December 17, 2020, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> the reason is: if it is not, and the encoding of all 0s happens to be used,
> and that happens to be SUBVL=4, predicate=Xxx blah blah
> then what will happen on a v3.B POWER10 system that does not have SV?
> *no trap will be raised and the standard instruction will be executed*.

no, an illegal instruction trap will occur, since those encodings are
specifically defined in the OpenPower v3.1 spec to be illegal instructions
-- not an invalid variation of a defined instruction. There *is no*
corresponding standard instruction to be executed.

> > You don't need to specially turn VL off, it's just ignored if all
> > inputs/outputs are set to scalar mode.
> and predication is off, and ffirst is off, and elwidth is default etc etc.
> i actually have difficulty describing this, because in the pseudocode,
> simulator *and* HDL, when VL=1 SUBVL=1 elwidth=default predicates=all1s etc
> etc. there are two ways to view this:
> * SV is "disabled" or
> * every augmentation feature does nothing even the for-loops are for i in
> range(1) and whilst SV is technically still active it isn't actually doing
> anything...
> *yet it is still running*.  which is very weird, and i have no idea how to
> succinctly put this.

SV is active, since you just executed an instruction from the SVP64
instruction block. that instruction just so happens to have identical
effect to the non-prefixed version, but that doesn't matter here. This is
just like how you could execute `fmv f3, f3` which has equivalent effect to
`nop` but it is not `nop`, it is a fp instruction.


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