Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Dec 16 22:53:14 GMT 2020
On Wednesday, December 16, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> ok summary changes this afternoon:
> * made a note that the 24 bits as all zeros ahould be "SV quiescent".
this would allow for standard v3.1B to run "as usual" including *sigh* VSX.
you mentioned something about nop and how all 0s in the 24 bits "will not
work". if that is not the case then i would like svp64 to be changed so
that it does. e.g. the EXTRA2/3 fields if zero mean "scalar behaviour of
registers" and so on.
i cannot think of a reason at all why that would be impractical.
however is there an "external" reason why it should mot work? i did not
understand what you referenced "nop" in the chat today, can you elaborate?
even if there is and there is some redundant meaning i think it wise, as i
mentioned to Paul, that all 0s be a "switches off SV" compatibility to keep
IBM engineers happy.
yes of course VL should still be off as well (set to 1 which is the way to
set the VL for-loop to "for i in range(1)" which is of course duh scalar).
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