Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Dec 16 20:14:56 GMT 2020
ok summary changes this afternoon:
* made a note that the 24 bits as all zeros ahould be "SV quiescent". this
would allow for standard v3.1B to run "as usual" including *sigh* VSX.
this has implications for encodings. elwidth=DEFAULT shoukd be 0b00,
predication off (all 1s) should be 0b000 etc etc.
* elwidth=DEFAULT rather than elwidth=64bit is very important. processors
running in 32 bit mode, they need a way to be allowed to modify operations
to 32 bit not 64 bit. elwidth=64bit interferes with that.
* explained why predication 0b000 needs to be "all 1s i.e. predication is
* started on a R_EXTRA2 table but cannot work out the names so put in an
alternative table that puts a pseudocode fragment in. i will do a similar
one for EXTRA3 if you can check them jacob?
there was something else..
* 2pred Dest SUBVL is unnecessary. i went through the list. only mv is
"safe" to do that, and really only mv.zip and mv.unzip to be honest. these
can have special opcodes. see mv.vec page
* oh yes, swizzle: you missed that i envisaged that predicate mask
immediates is one of the options, making 7 not 6 iptions.
without that as an option then the only way to work out SUBVL would be to
decode the swizzle (because any predicated out XYZW would need to increment
SUBVL). that would impact the 3rd phase of the instruction decoder and i
would strongly prefer that not to happen.
err yeah that's all :)
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