Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Dec 16 09:39:34 GMT 2020
ok went through the new additions, jacob, and you probably saw
already, just a summary:
* 2pred DEST SUBVL. evaluated, conclusion: no. makes no sense.
mv.vec covers it. details here
* 2pred and 1pred are so different that they really need separate
tables. actually a case could be made for having 3:
- dest, src1, src2, src3 (2 bit for reg expansion)
- dest, src1, src2 ( 3 bit for reg expansion)
- dest, src (2/3 bit - TODO decide - extra stuff
for dest elwidth etc)
* two tables R_EXTRA2 and R_EXTRA3
- TODO, should these be part of 2 tables
* i really, REALLY do not understand the naming. it is flat-out
impossible for me, due to what i am increasingly beginning to
recognise (after "only" 40 years) is a form of dyslexia, to interpret
the names. the old SVPrefix meaning which referred to bits was dead
* reduction of table names by reducing verbosity of descriptions. i
use a very small screen for viewing the wiki pages: editing and just
reviewing is a pain. the more words, the harder it is to understand.
i think that's everything, meeting in 20 mins.
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