[Libre-soc-dev] ecc memory without extra memory chips or extra i/o pins

Jacob Lifshay programmerjake at gmail.com
Wed Dec 16 06:41:05 GMT 2020

I think it might be a good idea to have a new layer between the soc and the
ddr memory interface that adds support for ecc by reserving 1/9 of the
bytes for error correction. This would help give our soc extra reliability
potentially allowing more people to use it for things like cubesats or
other places where special radiation hardened processes are overkill, but
preventing memory bit flips is desired.

I don't expect it to be very hard to add since hamming codes are relatively
simple, additionally the performance impact wouldn't be too bad since we'd
usually be reading/writing a whole cache line anyway and since a
significant part of the memory latency is the initial row/column access
time, not the data transfer rate.

we could also have ecc on the internal caches since those have a smaller
incremental cost. the icache and other read-only caches would only require
parity since we can just discard/reload the cache line upon error detection.

What do you think?


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