[Libre-soc-dev] daily kan-ban update 06AUG2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Thu Aug 6 18:52:29 BST 2020
On Thu, Aug 6, 2020 at 6:45 PM Cole Poirier <colepoirier at gmail.com> wrote:
> * MUL unit tests
> * Diagram prioritization bug completed for luke to now assess
> * Started translation of microwatt mmu.vhdl into soc/src/experiment/mmu.py
> I'm definitely misinterpreting some VHDL into incorrect nmigen
> structures, but I figured that you can help correct my course here
hmmm i've found that it's slow work but it's necessary to have the
actual vhdl open at the same time, and to "be" the person that's doing
also: much of the work can be done with a few choice
global/search/replaces. ": std_ulogic_vector(63 downto 0);" can be
global/search/replaced with " = Signal(64)" for example.
note that anything in a "rising edge" block **MUST** be "sync +="
> I've pasted the whole of mmu.vhdl as comments in mmu.py, and am
> translating clause by clause, interleaved with the vhdl comments, into
> nmigen. Can I commit this and get some help?
again: i believe i have said this about 5 times already, so you should
know by now that you do not need to ask when committing code that you
*know* is unused and cannot do "damage". so as jacob says (message
just came in when writing this): please just commit it, don't keep
also this time remember to do "git push".
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