[Libre-soc-dev] daily kan-ban update 04aug2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Aug 5 13:17:34 BST 2020
On Wednesday, August 5, 2020, Jacob Lifshay <programmerjake at gmail.com>
> Posting to libre-soc-dev since we should finally get around to moving
> Attended the openpower virtual coffee meeting which has been moved to
thank you for the notification on the list last night, i didn't realise the
decision had been made already.
yesterday i added DMI "step and regdump" to the litex sim.py
this allows a full cycle accurate comparison of libresoc against microwatt,
running the exact same binary.
that in turn allowed me to find and fix *yet another LD/ST* related bug:
this time, both ISACaller and the HDL had byte-reversal flipped. now
sorted, this explains why none of the qemu LD/ST tests worked.
however this was *still* not enough and it turns out that litex wishbone
64-to-32 arbiter when sel is not all 1s is faulty.
this has never really been detected before in litex because (A) most uses
of litex are 32 bit and (B) most uses of litex use a L1 cache with full
bandwidth read/writes (sel all 1s or with no byte level granularity).
i have a bugreport outstanding with florent about it.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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