[Libre-soc-dev] div fsm pipeline
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Aug 5 11:13:57 BST 2020
On Wed, Aug 5, 2020 at 5:03 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> Posting to libre-soc-dev since we should finally get around to moving
> I'm going to try to post to libre-soc-dev instead of
> libre-riscv-dev whenever I start a conversation.
a way to fix that is to put the other list into read-only mode
> Attended the openpower virtual coffee meeting which has been moved to tuesdays.
> Finally fixed the final bugs in the FSM-based div pipeline, all tests
> pass so I declare it completed!
hurrah. let's take a look, and run it through synth, and through
test_issuer.py. i've initiated the coriolis2 synth (it'll take 90+
minutes with my laptop speed-limited to not overheat)
one thing i notice that's missing - and is the reason why i referred
you (twice) to the microwatt div FSM - is that the microwatt FSM spots
opportunities for dropping 8 bytes of zeros in a cycle. that's a
*lot* of unnecessary cycles dropped which could save a lot of
> Found the cause of the mysterious test failures:
> Luke, what do you think is appropriate payment for the div pipeline?
well... you're not going to like it: it's been 3(?) months however
NLNet's budget allocations are based on productivity, not "time".
however the program_instruction_analyser was / is an extremely useful
additional dependency that was a key integral part of that, so should
definitely have a separate bugreport and budget allocation for it.
(btw about pia: it occurred to me that if taken further it could
actually become the basis of a cycle-accurate PowerISA simulator at
the div pipeline itself is not "wasted code" - we'll likely need it
later (although we have a decision to make on that: it may be better
to lay down multiple FSMs).
it's complicated in other words: we'll have to go through it.
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