[Libre-soc-bugs] [Bug 604] ISACaller simulator needs RADIX MMU support

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=604

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
design discussed here

http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-March/002061.html

RADIX Mem class to be added as an option that has a Mem class as a member
instance

and treats that as "Physical" memory.

exact same API.

class RADIXMem:

       self.mem = Mem()

    def ld(.....)

    def st(.....)

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