[Libre-soc-bugs] [Bug 605] Extend ECP5_FPGA wiki page with JTAG testing/boot procedure for Libre-SOC test chip

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Mon Mar 1 18:51:57 GMT 2021


--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Cole Poirier from comment #0)
> Once #517 JTAG STLINKv2 to FPGA connection guide wiki is complete:
> * lkcl to outline Libre-SOC test chip boot via jtag procedure for testing on
> FPGA before the test ASIC is taped-out

in the README is the version for sim.py

the FPGA and ASIC variant is near-identical.

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