[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #20)
> Hello,
> 
> I've commited d35e748 which provides correct block netlist integration.

star.

> 
> To integrate a block, asides from the layout you have to provide :
> 
> * A Verilog blackbox netlist ("machin.v") for Yosys.

i am investigating if there is an easy way for nmigen to apply
user attributes to modules.  this would do the same job.


> * A VHDL hollow netlist ("machin.vbe") for blif2vst and Coriolis
>   at large.
> 
> Concerning the use in symbolic mode, we would need a symbolic abstract
> view of the SRAM block.

otherwise the burden of even basic syntax checking falls entirely to
you and Staf.

> This is not very complicated, but still needs
> a modicum of time. And as it has a bit complex interface than the
> I/O pads, I leave it to the initiative of Staf.

Staf i think i will assign some budget to this task, to help with that.

> And to use the Coriolis in full compliance we should also add a diode
> (dio_x0) to the symbolic library nsxlib.
> 
> The layout integration is not completed yet, but in good way.

super.

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