[Libre-soc-bugs] [Bug 502] determine SRAM block size and implement it

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=502

--- Comment #20 from Jean-Paul.Chaput at lip6.fr ---
Hello,

I've commited d35e748 which provides correct block netlist integration.

To integrate a block, asides from the layout you have to provide :

* A Verilog blackbox netlist ("machin.v") for Yosys.
* A VHDL hollow netlist ("machin.vbe") for blif2vst and Coriolis
  at large.

Concerning the use in symbolic mode, we would need a symbolic abstract
view of the SRAM block. This is not very complicated, but still needs
a modicum of time. And as it has a bit complex interface than the
I/O pads, I leave it to the initiative of Staf.

And to use the Coriolis in full compliance we should also add a diode
(dio_x0) to the symbolic library nsxlib.

The layout integration is not completed yet, but in good way.

Best,

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