[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #90 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/180nm_Oct2020/2020-09-30_19-13.png

hmmm, jean-paul: some of the pins are coming in from almost 100% the
opposite side.  it seems that there is no... "weighted influence" on
where the cells associated with the I/O should be placed.

could this be solved algorithmically (with a "this I/O pad pin please
give it 5% weighting to put its cells closer to the pin" style algorithm)

or

should i simply go, "ok so we defined the IO pads, great, let's create
a Cell for ls180 with the I/O defined to be in specific places".

maybe even create a barrier ring just like in experiments7?

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