[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #89 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #88)
> > * Litex provides peripherals however the IO for UART and GPIO need to
> >   be routed *through JTAG*
> 
> Actually all IO should be routed through JTAG, thus also SDRAM, PWM, SPI, ...
> This allows standardized PCB testing without tester need to write power
> programs etc.

ngggghargh ok :)  i was hoping to get away with just GPIO and UART, to
at least "prove the concept" of the IOpad cells.  i picked GPIO and UART
because UART has one In-only and one Out-only IOpad, and GPIO is In-and-Out.

i set the precedent (parameterised functions) which make this possible,
so i should be able to add the others in 1-2 days.

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