[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #6 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #5)

I will divert two or three days to make the port of the chip/corona
plugin and the implementation of the new features. Would it be
possible to have a shrunk down core but still with all the
different I/O domains.

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