[Libre-soc-bugs] [Bug 506] 8x VDD VSS pins needed in ioring

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=506

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #4)
> Actually for the 0.18um tape-out the core voltage will be 1.8V and the IO
> voltage 3.3v.

ah.  that's why i asked about level-shifting.

this would imply that it would be best to also have env.setGROUND() take
a dictionary and env.setPOWER() also.

so just to be clear: *even though* the pxlib drop-in replacement is in
fact a drop-in replacement, is it the case that the IOpads are designed to:

* take 3.3v IO pad voltage supply
* but, accept an input signal at a 1.8v supply, to output 3.3v at the pad?
* and, convert an incoming pad voltage to the 1.8v "core'?

is that correct?  let's take an example:


  spisdcard_miso : pi_px
  port map ( ck   => cki      # ignore that this should be spisdcard_clk
           , pad  => spisdcard_miso         # to pad, @ 3.3v
           , t    => spisdcard_miso_core    # from core, @ 1.8v
           , vdde => vdde                   # this is IO GND?
           , vddi => vddi                   # this is core GND?
           , vsse => vsse                   # pad 3.3v IOVSS?
           , vssi => vssi                   # core 1.8v COREVSS?
           );


is that right?


> So separate supply have to also be foreseen for the VDDIO and
> VSSIO.

ok this i would be *very* happy to see, it is what i expected,
i was just surprised not to find it, and hadn't mentioned it
because you said "no there are no level-shifters".


>  Let's also take 2 VDDIO/VSSIO pairs on each side for the moment. This
> may be reduced in the future to one pair on each side.

actually... if it is not too inconvenient i would very much like to see proper
allocation of different number - and type - of VDDIO/VSSIO right now.

in particular, it may be a good idea to separate SDRAM IO VSS/VDD to stop
possible power-spikes from other peripherals if they were on the same
power ring.

(even if both general IO VSS *and* SDRAM IO VSS are both 3.3v, it is still
good practice to separate them).


Staf: can the pxlib that you are designing go as low as an external
IO voltage of 1.8v?  if so that would be absolutely fantastic because
a separate VDD_SDCARD can be created which would allow for an external
PMIC (Power Management IC) to drop the SD/MMC Card I/O voltage to 1.8v
under software control.

(e.g. the AXP-209 PMIC can be controlled by I2C commands to tell different
IO voltage domains to change voltages).



> To reduce bond wire loop area it is also best to put the VDD/VSS pins next
> to each other in the IO-ring.

good point.

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