https://bugs.libre-soc.org/show_bug.cgi?id=324 --- Comment #41 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> --- btw jacob i noticed that on qemu, divw sets RT=RA when RB=0. can you check that behaviour on POWER9? -- You are receiving this mail because: You are on the CC list for the bug.