[Libre-soc-bugs] [Bug 324] create POWER DIV pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jun 30 11:57:51 BST 2020


--- Comment #40 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #39)

> self.o.op is not defined, which is why i tried to find something to set it
> to.
> if you can run the unit test "python3 fu/div/test/test_pipe_caller.py" and
> investigate that would be really helpful.

i went over everything that gets set up as part of self.o.core and
it looks like all parts of DivPipeCoreInputData are established:

class DivPipeCoreInputData:

        self.dividend = Signal(bw + fw, reset_less=reset_less)
        self.divisor_radicand = Signal(bw, reset_less=reset_less)
        self.operation = DP.create_signal(reset_less=reset_less)


        comb += core_o.operation.eq(int(DivPipeCoreOperation.UDivRem))

dividend and divisor:

        dividend_o = core_o.dividend
        divisor_o = core_o.divisor_radicand

these also get set up.  so i believe the self.o.op.eq() - presumably
intended to be self.o.core.eq() - is redundant.

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