[Libre-soc-bugs] [Bug 382] nmigen wishbone Memory object needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=382

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=nmigen-soc.git;a=blob;f=nmigen_soc/wishbone/sram.py;h=de5c15d551c081a224590ee4ba8706ca3d2d7547;hb=refs/heads/wishbone_interconnect

i've created a repository nmigen-soc, tracking harry ho's repo
https://github.com/HarryMakes/nmigen-soc

i can't stand branches: they always end up making a mess, indicating divergence
and communication delay.

we need to move much faster.

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