[Libre-soc-bugs] [Bug 407] XICS interrupt controller is needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=407

--- Comment #12 from Cole Poirier <colepoirier at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> no it's not that one - XICS is like the PLIC for RISC-V.  it's the central
> (generic) "hub" for interrupts and defines the layout of in-memory registers.
> 
> for example for the source layer (microwatt xics.vhdl):
> 
> -- Register map
>     --     0  : Config
>     --     4  : Debug/diagnostics
>     --   800  : XIVE0
>     --   804  : XIVE1 ...
>     --
>     -- Config register format:
>     --
>     --  23..  0 : Interrupt base (hard wired to 16)
>     --  27.. 24 : #prio bits (1..8)
>     --
>     -- XIVE register format:
>     --
>     --       31 : input bit (reflects interrupt input)
>     --       30 : reserved
>     --       29 : P (mirrors input for now)
>     --       28 : Q (not implemented in this version)
>     -- 30 ..    : reserved
>     -- 19 ..  8 : target (not implemented in this version)
>     --  7 ..  0 : prio/mask
> 
> 
> and for the presentation layer there's something similar.
> 
> so the interrupt wires come in from a "source" (a single bit,
> each given a number), and it is possible to set the individual
> priority (by writing to the XIVEnnn register).
> 
> then the "presentation" layer receives a notification about one
> of those, and generates - to the core - a *single* interrupt to
> say "please come and look at the presentation layer registers
> XIRR and MFRR to find out which one of the source interrupts
> has occurred".
> 
> from the microwatt source code, _reading_ the XIRR register actually
> clears the interrupt.
> 
> so that's how it fits together.

Ok, so if I understand correctly xics is the internal interrupt infrastructure
and the "LoPAR interrupt controller [is something] platforms may chose to
virtualize or to provide the PowerPC External Interrupt option."
(https://github.com/OpenPOWERFoundation/Linux-Architecture-Reference/blob/master/LoPAR/ch_interrupt_controller.xml)
That deals with PCIE interrupts? Sorry I'm still a little confused...

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