[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Fri Jul 24 15:04:57 BST 2020


--- Comment #133 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Samuel A. Falvo II from comment #132)
> Actually, removed one.  ;)  Walk through the code again.  :)  That's why I
> wrote the function: to automate the error-checking, so that I wouldn't run
> into this issue again.

Just to illustrate what I mean, with your changes, this is what I get when I
run the trap proof now.  Note that the bit numbers are wrong relative to what's
in the source code, and they're demonstrably out of order in the exception
report, even though they're *in* order in the source code.

ERROR: test_ilang (proof_main_stage.TrapMainStageTestCase)
Traceback (most recent call last):
line 272, in test_ilang
    vl = rtlil.convert(Driver(), ports=[])
  File "/home/kc5tja/git/libre-soc/nmigen/nmigen/back/rtlil.py", line 1056, in
    fragment = ir.Fragment.get(elaboratable, platform).prepare(**kwargs)
  File "/home/kc5tja/git/libre-soc/nmigen/nmigen/hdl/ir.py", line 39, in get
    obj = obj.elaborate(platform)
line 126, in elaborate
    comb += field(expected_msr, MSRb.TEs, MSRb.TEe).eq(0)
  File "/home/kc5tja/git/libre-soc/soc/src/soc/consts.py", line 36, in field
    return r[field_slice(start, end)]
  File "/home/kc5tja/git/libre-soc/soc/src/soc/consts.py", line 22, in
    raise ValueError(
ValueError: start (10) must be less than end (9)


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