[Libre-soc-bugs] [Bug 325] create POWER9 TRAP pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=325

--- Comment #132 from Samuel A. Falvo II <kc5tja at arrl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #126)
> 1) comments are added which "explain why".  removing comments is detrimental
>    to communication and code maintenance.

My aim was to remove only those comments I felt were addressed solely to me.  I
wasn't clear which comments qualified.

> 2) is it now clear what i said: that the python slice numbering has to
>    be LHS < RHS?  in each and every case (including TEs and TEe but

That has always been clear, and has always been the intention.  However, bugs
remain despite my best efforts.

>    now where field_slice is used 30, 31 you've *introduced* a bug)

Actually, removed one.  ;)  Walk through the code again.  :)  That's why I
wrote the function: to automate the error-checking, so that I wouldn't run into
this issue again.

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