[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #18)
> Hello Luke,
> 
> I'm starting to work on:
>     soc/src/soc/simple/test/test_issuer.py
> 
> And, of course, I get problems. First, I updated all the libre-soc git
> repositories and re-installed them. Then I got into various errors
> with nMigen. The latest being:
> 
> Traceback (most recent call last):
>   File "./test_issuer.py", line 21, in <module>
>     from soc.simple.test.test_core import (setup_regs, check_regs,
>   File ".../soc/src/soc/simple/test/test_core.py", line 28, in <module>
>     from soc.fu.alu.test.test_pipe_caller import ALUTestCase
>   File ".../soc/src/soc/fu/alu/test/test_pipe_caller.py", line 5, in <module>
>     from nmigen.sim.cxxsim import Simulator
> ModuleNotFoundError: No module named 'nmigen.sim.cxxsim'

ah right.  yes.  that relies on the nmigen cxx_sim branch, apologies.
let me sort that with a try/except Import.

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