[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jul 21 12:50:56 BST 2020


--- Comment #18 from Jean-Paul.Chaput at lip6.fr ---
Hello Luke,

I'm starting to work on:

And, of course, I get problems. First, I updated all the libre-soc git
repositories and re-installed them. Then I got into various errors
with nMigen. The latest being:

Traceback (most recent call last):
  File "./test_issuer.py", line 21, in <module>
    from soc.simple.test.test_core import (setup_regs, check_regs,
  File ".../soc/src/soc/simple/test/test_core.py", line 28, in <module>
    from soc.fu.alu.test.test_pipe_caller import ALUTestCase
  File ".../soc/src/soc/fu/alu/test/test_pipe_caller.py", line 5, in <module>
    from nmigen.sim.cxxsim import Simulator
ModuleNotFoundError: No module named 'nmigen.sim.cxxsim'

Currently I use nMigen d714d78 (HEAD of 14/07/2020).
I did git update, but even with the latest one, I can't locate any
nmigen.sim.cxxsim module... What do I do wrong. Could you pinpoint me
the working commit of nMignen ?

Best regards,

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