[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #13 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
interesting!  a "yield" was missing which was only caught by cxxsim

commit fc256a3df6502d725131a3aa979c2a88aa695d3d (HEAD -> master)
Author: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Date:   Sun Jul 19 15:53:36 2020 +0100

    fix bug in alu_fsm.py found by cxxsim: missing one cycle hold of ready_i

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