[Libre-soc-bugs] [Bug 417] FSM-based ALU example needed (compliant with ALU CompUnit)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=417

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)

> quite big.  op_sim() however is short enough to cut/paste 
> although a tidy-up (to use op_sim only) would involve setting
> up dut.oper_i *outside* of op_sim.  i might do that shortly.

no, i know why i didn't do that (why i cut/paste it), it's because
of this:

    if not imm_ok or not zero_a:
        yield dut.rd.go.eq(0b11)

however now that i look at it, the test in op_sim() is a bit
borked.  it should be more like:

    if not imm_ok or not zero_a:
        go_rd = 0b1
        if not imm_ok:
            go_rd |= 0b10

        yield dut.rd.go.eq(go_rd)

something like that, or possibly

        go_rd = 0
        if not imm_ok:
            go_rd |= 0b10
        if not zero_ok:
            go_rd |= 0b1

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