[Libre-soc-bugs] [Bug 306] Formal Correctness Proof for ALU pipeline

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=306

--- Comment #9 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
from commit git diff 685b7 769a8, samuel did this:

+        # Output context is the same as the input context.
+        comb += Assert(dut.o.ctx != dut.i.ctx)

this is the reasonable expectation: both are Records.  should it be
ok to Assert that one Record's contents equals the contents of another?

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