[Libre-soc-bugs] [Bug 306] Formal Correctness Proof for ALU pipeline

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Jul 14 21:29:10 BST 2020


Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
         Resolution|FIXED                       |---
           Assignee|mtnolan2640 at gmail.com       |kc5tja at arrl.net
                 CC|                            |mtnolan2640 at gmail.com
             Status|RESOLVED                    |IN_PROGRESS

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
assigning to Samuel for review of formal_main_stage.py up to this point:

        # Assert that op gets copied from the input to output
        for rec_sig in rec.ports():
            name = rec_sig.name
            dut_sig = getattr(dut.o.ctx.op, name)
            comb += Assert(dut_sig == rec_sig)


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