[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #57)
> (In reply to Luke Kenneth Casson Leighton from comment #55)
> > https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/23
> 
> I've just made pushed various commit that *may* solve the problem.
> I'm not totally sure as there are still off-side pins that prevents
> me to go all the way.
> 
> I took the liberty to beautify a little doDesign.py, hopefully respecting
> you Python style. I know that for IO pin specification, the list is not
> PEP8 compliant, but I think that a "spreadsheet" presentation with clearly
> aligned columns is better to immediately spot missing parameters or errors.

what i would like, there, is wildcard matching e.g. starts with "oper_i" or
ends with "_ok" and the pincount to be obtained from the object.

this will reduce 30-40 lines per block down to *five* and at the same time
greatly increase clarity.


> 
> I also removed the utils module, as now Coriolis should supply equivalent
> features.

ah excellent, glad you liked it.

Config is neat, ehn? :)


the number of oper_* pins is far too large.  this is the "expansion" of the
instruction for convenience.  an example is the 64 bit immediate.

basically i am going to have to do "subset instruction decoders" that are
*inside* mul0, *inside* alu0 and so on.

i have to find time to do that.

until then i think we stop with the floorplan version and go with "flat".

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