[Libre-soc-bugs] [Bug 199] Layout using coriolis2 main core, 180nm

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=199

--- Comment #57 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Luke Kenneth Casson Leighton from comment #55)
> https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/23

I've just made pushed various commit that *may* solve the problem.
I'm not totally sure as there are still off-side pins that prevents
me to go all the way.

I took the liberty to beautify a little doDesign.py, hopefully respecting
you Python style. I know that for IO pin specification, the list is not
PEP8 compliant, but I think that a "spreadsheet" presentation with clearly
aligned columns is better to immediately spot missing parameters or errors.

I also removed the utils module, as now Coriolis should supply equivalent
features.

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