[libre-riscv-dev] wishbone does not have byte-enable (but it does have user-tags)

[Luke Kenneth Casson Leighton]

http://cdn.opencores.org/downloads/wbspec_b4.pdf

one of the things that i have assumed is possible to do in wishbone is
to have a bank of byte-enable lines for the memory read/write
requests.  am i correct in thinking that this is what "sel" (as an
array) is for?

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/wishbone.py;hb=HEAD#l16

also i've noticed that there is the concept of user and cycle "tags"
which can be optionally added.  this would give us a way to do
cache-line tagging and many other things.

l.