[libre-riscv-dev] daily kan-ban update 19jul2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Jul 20 00:19:17 BST 2020

On Sunday, July 19, 2020, Yehowshua <yimmanuel3 at gatech.edu> wrote:

> >
> > in our case that's 17,000 flattened signals.
> Verilator retains the hierarchy of whatever it consumes.
> SO you’ll get a hierarchical CPU and flat peripherals.

thank goodness for that.

many of the pipeline signals have not been given globally unique names,
meaning there's dozens of duplicate "ready_o" etc. and more.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list