[libre-riscv-dev] Signal names for trap pipeline??

Samuel Falvo II sam.falvo at gmail.com
Sat Jul 18 03:09:39 BST 2020

On Fri, Jul 17, 2020 at 5:58 PM Samuel Falvo II <sam.falvo at gmail.com> wrote:
> I'm running into an irreconcilable property violations with the formal
> properties for the trap main stage.

Please disregard; I just spotted the convenience assignments in the
TrapInputData class.  Egg, meet face.

Samuel A. Falvo II

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