[libre-riscv-dev] Signal names for trap pipeline??

Samuel Falvo II sam.falvo at gmail.com
Sat Jul 18 01:58:55 BST 2020

I'm running into an irreconcilable property violations with the formal
properties for the trap main stage.

I'm noticing that there's repeated references to SRR0 and SRR1
registers in https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;h=325fb373546673df3ec19a15554e775bcc6fe9a9;hb=HEAD;
however, after spending about 30 minutes hacking away at what might be
the cause, I realized after reviewing the graphs in GTKWave that I
don't see these signals in either the top or the DUT module signals.

Looking in https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/pipe_data.py;h=d2de8552a62a55bada4a5e83726c273ef943ac83;hb=HEAD
seems to confirm my suspicion that neither srr0 nor srr1 actually
exist; they are (confusingly) called fast1 and fast2.  Double-checking
GTKWave's signal lists confirms that fast1 and fast2 exist.

Can anyone please advise on how to proceed?  I see several ways of
resolving this going forward, but I need input from others:

1.  Rename fast1 and fast2 to srr0 and srr1, or,
2.  Keep fast1/fast2 and rebind them to srr0/srr1 in the main_stage.py
and prove_main_stage.py files, or,
3.  ...?


Samuel A. Falvo II

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