[libre-riscv-dev] Markdown on the wiki?
Samuel Falvo II
sam.falvo at gmail.com
Sat Jul 18 02:19:07 BST 2020
Sorry; just getting to this email now. You'd think that being
unemployed would give you loads of time. And, maybe it does, but only
after you clear your queue of other honey-dos and deliverables that's
queued up for others over time. Uugh.
I can appreciate why people say that being "retired" is exhausting. ;)
On Wed, Jul 15, 2020 at 10:13 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> i updated the page you started, a bit more, this morning. you should be getting the impression now as to why i described this pipeline as dead simple to start from, because the code itself in spr main_stage.py really does not actually do very much.
Thanks; I'll take a read later this evening.
> no regfile reading, no decisions, no instruction decoding: nothing. its *sole* job is to process its inputs and create some outputs. it doesn't even know which registers that data actually comes from or goes to because *that is not its responsibility*.
Yeah, and I'm getting a lot of ideas for my future KCP53000
refinements as well. In *theory*, it should be possible to use the
exact same combinatorial building blocks in a single-issue design as
it would in a pipelined, multi-issue design; only the wiring between
the blocks would need to be handled differently. (Of course, theory
and reality are only theoretically related; still, I can see how this
would significantly *ease* the prospect of re-architecting the design
if ever became necessary.)
And if the libresoc becomes affordably available for me to hack with,
maybe I can design a CPU card around it for the Kestrel-3. (Of
course, I'll need to migrate all the code currently running in M-mode
to U-mode first.)
Samuel A. Falvo II
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