[libre-riscv-dev] daily kan-ban update 11jul2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jul 12 02:56:58 BST 2020
On Saturday, July 11, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> still the biggest next milestone is being able to select littlend/bigend
> code in order to run microwatt unit tests. still thinking that through.
for now i have set up a module with a single global flag that everything
uses. this can be changed later to respect the appropriate MSR bit.
i identified that in PowerDecoder the instruction byte swapping was
inverted. correcting this brought the decoder into line with qemu and with
microwatt test binaries.
the next phase was to track down a bug in core.py where rather than take
the conditional output from the CompUnit i had connected directly to the
pipeline ALU output.
the pipeline output obvuously changes depending on what cycle is currently
being executed, resulting in data corruption.
whereas the CompUnit Manager's entire job is to latch that data at the
correct point in time, then present it to the Regfile Bus on request.
this allowed me to progress to another bug that i will investigate
tomorrow. there may be a ST instruction missing from the CSV files, i have
to track it down.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
More information about the libre-riscv-dev