[libre-riscv-dev] Re-Introduction

Samuel Falvo II sam.falvo at gmail.com
Thu Jul 9 05:07:09 BST 2020

Hello everyone, again!

Way back in "þe auld dayes"[1], I wanted to contribute to this project.  I
introduced myself, I signed up, and then, my responsibilities at my day-job
changed in a way which, frankly, drained all my energy for the day.  So, I
ended up disappearing for some time, except the occasional question or
comment in e-mail.

Well, recently, I found myself laid off from work and am now in a position
where I can help contribute more positively to this project again.

Here's some data about me (format shamelessly stolen from the members page):

   - Experience in amateur HDL projects (Kestrel-3 homebrew computer
   concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
   design.  Extensive experience with test-driven development, Python, RISC-V
   assembly language, and Forth.  Very comfortable with nMigen, but still
   learning things.
   - Interests: Forth, Common Lisp, Scheme, assembly language,
   {Astro|Semiconductor-}physics, astronomy, martial arts, furry
   - Websites: https://hackaday.io/project/170581-vdc-ii ,
   https://kestrelcomputer.github.io/kestrel/ ,
   - Public Repositories: https://github.com/sam-falvo ,
   - Availability: approximately 20 hrs/wk, circumstances permitting.

1.  Yes, þe is actually the correct spelling; "ye" was also used, but was
still pronounced "thee" and not "yee".

Samuel A. Falvo II

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